1. Field of the Invention
The present invention relates to a plasma processing apparatus for performing plasma processing on a substrate to be processed, such as a semiconductor wafer.
2. Description of the Related Art
Conventionally, in a semiconductor manufacturing process, etching apparatus are used to form a contact hole in an insulating film formed in a surface of, for example, a semiconductor wafer (which will be referred to as only a wafer). Among those apparatuses, an etching apparatus of a parallel plate type in which a pair of electrodes are provided in a processing chamber is particularly excellent in processing uniformity and has advantages in that the apparatus structure is relatively simple. Therefore, a large number of etching apparatuses of this type are used.
A conventional etching apparatus of the parallel plate type generally used is arranged such that a pair of plate type electrodes are provided opposite to each other in the processing chamber, for example, as well-known from Japanese Patent Application KOKAI Publication No. 62-69620. In this apparatus, a wafer as a substrate to be processed is mounted on an electrode in the lower side (i.e., a lower electrode), and an etching gas is introduced into the processing chamber. Simultaneously, a high frequency electric power is supplied to the lower electrode, thereby generating a plasma. The etching gas is dissociated thereby generating etchant ions which etch the insulating film on the wafer.
In the processing for etching this kind of insulating film, as the integration of the semiconductor device becomes higher, it is required that the processing be finer, the processing speed be more improved, and the processing be done more uniformly. Therefore, the density of a plasma generated between electrodes should be higher.
In this respect, in the plasma apparatus disclosed in Japanese Patent Application KOKAI Publication No. 62-69620, an insulating member is provided at a peripheral portion of one of the pair of electrodes, in order to prevent diffusion of a generated plasma and to concentrate the plasma between the electrodes, so that a narrow distance structure is constructed in which the distance between the insulating member and the other one of the electrodes or another insulating member is set to 70% or less of the distance between the opposing electrodes. Thus, diffusion of the area where a plasma is generated is prevented.
However, the technique disclosed in Japanese Patent Application KOKAI Publication No. 62-69620 has an object of manufacturing a DRAM of approximately 256k to 1M, and therefore does not apply to the recent aspect of manufacturing a highly integrated device, such as, a DRAM of 64M. Specifically, to practice finer etching at a higher speed, for example, the pressure in a processing chamber must be more reduced (i.e., the degree of vacuum must be increased). The prior art has been achieved by supposing a pressure (or degree of vacuum) of approximately 5 Torr to 3 Torr, and it is difficult to prevent diffusion of a plasma area at a higher degree of vacuum than that pressure, so that the etching rate cannot be improved. In addition, there is a possibility that a plasma diffused from between electrodes may directly cause spattering on an inner side wall of a processing chamber, thereby generating contamination. Further, in the narrow distance structure, those portions of the insulating member which are close to the narrow-distance area have a higher plasma density than that in the central portion of the electrodes, so that the processing is not uniform. Further, in the narrow-distance structure, an exhausted gas such as an etching gas or the like may remain in the processing area, so that desired processing cannot be performed.
Although, an ECR etching apparatus has been proposed as a technique suitable for manufacturing a DRAM of 64M, this technique is said to have a limitation that etching is limited to wafers of 6 inches and 8 inches at most, in view of its processing area, and therefore, this technique will not be suitable for a wafer of a large diameter in the future, e.g., a wafer of 12 inches.
Meanwhile, as for the upper electrode, there are several cases that an insulating member is provided at a peripheral portion of an upper electrode, to support the upper electrode on the inner wall of the processing chamber or to cover bolts or the likes used for supporting the upper electrode. In addition, as for the lower electrode, there is a case that a focus ring made of an insulating member is provided at a peripheral portion of the lower electrode, in order to increase the incidence efficiency.
Reaction products generated during the processing may stick to surfaces of the insulating members. If these products are left unchanged, they pollute the inner space of the processing chamber, lowering the yield and shortening the cleaning cycle, so that the working time of the apparatus may be shortened and the production efficiency may be lowered. Therefore, it is necessary to prevent reaction products from sticking thereto and to remove reaction products, by using any means.
Reaction products of this kind which are generally known have a poor tendency to stick or tend to be easily removed if once have stuck when the temperature is high. Therefore, in conventional cases, a heater which generates heat by electric conductance is installed on the surface or the back surface of a portion to which reaction products easily stick and the temperature of the portion is increased, thereby to prevent reaction products from sticking thereto.
However, if a heater of such a electric conductance type is installed, high frequency noise may be induced in the electric conductive path, or a magnetic field may be generated by a current flowing through the electric conductance path of the heater. Therefore, the plasma in the processing chamber may be disordered, thereby causing problems when performing predetermined etching processing. Further, installation of an optional heater complicates routing of electric conductance paths and results in increases in costs.